The present invention relates to a layered board (hereinafter referred to as a “buildup board”) which includes a core layer and a buildup layer overlaid thereon.
The buildup boards have conventionally been used for laptop personal computers (PCs), digital cameras, servers, cellular phones, etc, to meet miniaturization and weight saving demands of electronic apparatuses. The buildup board is manufactured by using a double-sided printed board or a multilayer printed board as a core, and overlaying an interfacially connected buildup layer (which is a laminate of an insulating layer and a wiring layer) on both surfaces or a single surface of the core through the microvia technology (see Japanese Patent Application Laid-Open No. 2003-218519).
An electronic component of a layered type such as the buildup board has the problems of delamination at a boundary between layers, cracks, and warping of the electronic component due to a difference in coefficient of thermal expansion between a plurality of bonded layers.
The present applicant has proposed the technique for enabling the prevention of warping of a buildup board, delamination, etc, by controlling the coefficient of thermal expansion, the thickness, the modulus of longitudinal elasticity, etc, of each layer in the buildup board.
Japanese Patent Application Laid-Open No. 11 (1999)-112114 has proposed the technique in which a buildup board includes a closed curve pattern which surrounds a conductive pattern in a surface where an insulating layer is formed on a surface of a core layer to prevent cracks at the boundary of the conductive pattern in the insulating layer.
In addition, Japanese Patent Application Laid-Open No. 2003-7962 has disclosed the technique in which a semiconductor layered module employs different adhesives for bonding a board and a semiconductor chip and for bonding element modules each consisting of the board and the semiconductor chip to prevent separation between element packages, warping of the layered module, etc.
Japanese Patent Application Laid-Open No. 10 (1998)-144504 has disclosed the technique which, although not in an electronic component of a layered type, in a chip type thermistor surface-mounted to a board, prevents stress produced due to a difference in coefficient of thermal expansion between a board or an electrode on the board and solder from affecting the body of the thermistor through an external electrode of the thermistor to cause cracks in the thermistor body. In the technique, a conductive resin layer is formed between the thermistor body and the external electrode to relieve the stress applied to the thermistor body.
The buildup board is subjected to a temperature cycling test before it is shipped as a product. The temperature cycling test is performed to check whether or not normal operation is maintained even after cooling to a temperature of −65° C. and heating to a temperature of 150° C. are repeated a predetermined number of times, for example.
When sudden temperature changes are made in such a temperature cycling test, however, as shown in FIG. 17, shearing stress F is applied to a core layer 310 in its in-plane direction due to a difference in coefficient of thermal expansion between the core layer 310 and buildup layers 320, that is, a difference in a contraction amount or an expansion amount. The shearing stress F is mainly applied at the edges on the periphery of the core layer 310 (the outermost parts in the in-plane direction, particularly the corner parts) and may cause cracks 330 in the core layer 310. Especially when the core layer 310 is formed by using a carbon-based material (for example, CFRP) or a silicon-based material with a coefficient of thermal expansion significantly lower than that of the buildup layer 320, the shearing stress often excesses the breaking strength of the core layer 310 and the cracks easily occur.
The core layer 310 and the buildup layer 320 are bonded together with an epoxy adhesive which has the effect of relieving stress produced at the bonding parts. However, it has little effect of reducing the abovementioned shearing stress applied to the core layer 310.
In addition, it is difficult even for the techniques proposed by the present applicants and disclosed in patent applications mentioned above to prevent such cracks in the core layer due to the shearing stress.